View WM8768EDSR_693071.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w
24-bit, 192kHz 8-Channel DAC
DESCRIPTION
The WM8768 is a multi-channel audio DAC ideal for DVD and surround sound processing applications for home hi-fi, automotive and other audio visual equipment. Four stereo 24-bit multi-bit sigma delta DACs are used with oversampling digital interpolation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 192kHz are supported. Each DAC channel has independent digital volume and mute control. The audio data interface supports I2S, left justified, right justified and DSP digital audio formats. The device is controlled either via a 3 wire serial interface or directly using the hardware interface. These interfaces provide access to features including channel selection, volume controls, mutes, de-emphasis and power management facilities. The device is available in a 28-pin SSOP.
WM8768
FEATURES
* * * * * 8-Channel DAC with PCM. Audio Performance - 103dB SNR (`A' weighted @ 48kHz) DAC DAC Sampling Frequency: 8kHz - 192kHz 3-Wire SPI Serial or Hardware Control Interface Programmable Audio Data Interface Modes - I2S, Left, Right Justified or DSP - 16/20/24/32 bit Word Lengths Four Independent stereo DAC outputs with independent digital volume controls Master or Slave Audio Data Interface 2.7V to 5.5V Analogue, 2.7V to 3.6V Digital supply Operation 28 pin SSOP Package
* * * *
APPLICATIONS
* * * DVD Players Surround Sound AV Processors and Hi-Fi systems Automotive Audio
BLOCK DIAGRAM
VREFN VREFP DVDD DGND AGND VMID AVDD
VREFN VREFP
MCLK LRCLK BCLK DIN1 DIN2 DIN3 DIN4 DIGITAL AUDIO INTERFACE & DIGITAL FILTERS
STEREO DAC
LOW PASS FILTER
VOUT1L VOUT1R VOUT2L VOUT2R VOUT3L VOUT3R VOUT4L VOUT4R
STEREO DAC
LOW PASS FILTER
STEREO DAC
LOW PASS FILTER
STEREO DAC
LOW PASS FILTER
CONTROL INTERFACE
W
WM8768
WOLFSON MICROELECTRONICS plc w :: www.wolfsonmicro.com
TESTREF1
MC/IWL
MODE
MUTE
MD/DM
ML/I2S
Production Data, March 2005, Rev 4.1 Copyright 2005 Wolfson Microelectronics plc
WM8768 TABLE OF CONTENTS
Production Data
DESCRIPTION ................................................................................................................1 FEATURES......................................................................................................................1 APPLICATIONS ..............................................................................................................1 BLOCK DIAGRAM ..........................................................................................................1 TABLE OF CONTENTS ..................................................................................................2 PIN CONFIGURATION 28 PIN SSOP............................................................................3 ORDERING INFORMATION ...........................................................................................3 PIN DESCRIPTION - 28 PIN SSOP ...............................................................................4 ABSOLUTE MAXIMUM RATINGS..................................................................................5 RECOMMENDED OPERATING CONDITIONS ..............................................................6
MASTER CLOCK TIMING .......................................................................................................8 DIGITAL AUDIO INTERFACE - MASTER MODE ...................................................................8 DIGITAL AUDIO INTERFACE - SLAVE MODE ......................................................................9 MPU INTERFACE TIMING ....................................................................................................11
INTERNAL POWER ON RESET CIRCUIT ...................................................................12 DEVICE DESCRIPTION................................................................................................13
INTRODUCTION ...................................................................................................................13 PCM AUDIO DATA SAMPLING RATES................................................................................13 HARDWARE CONTROL MODES .........................................................................................14 DIGITAL AUDIO INTERFACE ...............................................................................................16 POWERDOWN MODES .......................................................................................................19 SOFTWARE CONTROL INTERFACE OPERATION.............................................................20 CONTROL INTERFACE REGISTERS ..................................................................................20
REGISTER MAP............................................................................................................32 DIGITAL FILTER CHARACTERISTICS ........................................................................33 DAC FILTER RESPONSES ..........................................................................................33
DIGITAL DE-EMPHASIS CHARACTERISTICS.....................................................................34
APPLICATIONS INFORMATION ..................................................................................35
RECOMMENDED EXTERNAL COMPONENTS ....................................................................35 RECOMMENDED EXTERNAL COMPONENTS VALUES .....................................................35 SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS .............................................36
PACKAGE DRAWING...................................................................................................37 IMPORTANT NOTICE ...................................................................................................38
ADDRESS: ............................................................................................................................38
w
PD Rev 4.1 March 2005 2
Production Data
WM8768
PIN CONFIGURATION 28 PIN SSOP
ORDERING INFORMATION
DEVICE WM8768EDS WM8768EDS/R WM8768GEDS WM8768GEDS/R Note: Reel quantity = 2,000 TEMPERATURE RANGE -25 to +85oC -25 to +85 C -25 to +85 C -25 to +85 C
o o o
PACKAGE 28-pin SSOP 28-pin SSOP (tape and reel) 28-pin SSOP (lead free) 28-pin SSOP (lead free, tape and reel)
MOISTURE SENSITIVITY LEVEL MSL3 MSL3 MSL3 MSL3
PEAK SOLDERING TEMPERATURE 260C 260C 260C 260C
w
PD Rev 4.1 March 2005 3
WM8768 PIN DESCRIPTION - 28 PIN SSOP
PIN 1 NAME MODE TYPE Digital input Control format selection 0 = Software control 1 = Hardware control DESCRIPTION
Production Data
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
MCLK BCLK LRCLK DVDD DGND DIN1 DIN2 DIN3 DIN4 ML/I2S MC/IWL MD/DM MUTE TESTREF1 VREFN VREFP VMID VOUT4L VOUT4R VOUT1L VOUT1R VOUT2L VOUT2R VOUT3L VOUT3R AGND AVDD
Digital input Digital input/output Digital input/output Supply Supply Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input/output Analogue output Analogue input Analogue input Analogue output Analogue output Analogue output Analogue output Analogue output Analogue output Analogue output Analogue output Analogue output Supply Supply
Master clock; 128, 192, 256, 384, 512, 768fs or 1152fs (fs = word clock frequency) Audio interface bit clock Audio left/right word clock Digital positive supply Digital negative supply DAC channel 1 data input DAC channel 2 data input DAC channel 3 data input DAC channel 4 data input Software Mode: Serial interface Latch signal Hardware Mode: Input Audio Data Format Software Mode: Serial control interface clock Hardware Mode: Audio data input word length Software Mode: Serial interface data Hardware Mode: De-emphasis selection DAC Zero Flag output or DAC mute input Test Pin DAC negative reference supply DAC positive reference supply Midrail divider decoupling pin; 10uF external decoupling DAC channel 4 left output DAC channel 4 right output DAC channel 1 left output DAC channel 1 right output DAC channel 2 left output DAC channel 2 right output DAC channel 3 left output DAC channel 3 right output Analogue negative supply and substrate connection Analogue positive supply
Note : Digital input pins have Schmitt trigger input buffers.
w
PD Rev 4.1 March 2005 4
Production Data
WM8768
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Digital supply voltage Analogue supply voltage Voltage range digital inputs Voltage range analogue inputs Master Clock Frequency Operating temperature range, TA Storage temperature after soldering Notes: 1. Analogue and digital grounds must always be within 0.3V of each other for normal operation of the device. -25C -65C MIN -0.3V -0.3V DGND -0.3V AGND -0.3V MAX +5V +7V DVDD +0.3V AVDD +0.3V 37MHz +85C +150C
w
PD Rev 4.1 March 2005 5
WM8768 RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analogue reference supply Analogue supply range Ground Difference DGND to AGND SYMBOL DVDD VREFP AVDD AGND, VREFN, DGND -0.3 TEST CONDITIONS MIN 2.7 2.7 2.7 0 0 +0.3 TYP MAX 3.6 5.5 5.5
Production Data
UNIT V V V V V
Note: Digital supply DVDD must never be more than 0.3V greater than AVDD for normal operation of the device.
ELECTRICAL CHARACTERISTICS
Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs, unless otherwise stated. PARAMETER Input LOW level Input HIGH level Output LOW Output HIGH Analogue Reference Levels Reference voltage Potential divider resistance VVMID RVMID VREFP to VMID and VMID to VREFN VREFP/2 100 V k SYMBOL VIL VIH VOL VOH IOL=1mA IOH= -1mA 0.9 x DVDD 0.7 x DVDD 0.1 x DVDD TEST CONDITIONS MIN TYP MAX 0.3 x DVDD UNIT V V V V Digital Logic Levels (CMOS Levels)
DAC Performance (Load = 10k, 50pF) 0dBFs Full scale output voltage SNR (Note 1,2,4) SNR (Note 1,2,4) SNR (Note 1,2,4) SNR (Note 1,2,4) A-weighted, @ fs = 48kHz A-weighted @ fs = 96kHz A-weighted @ fs = 192kHz A-weighted @ fs = 48kHz, AVDD = 3.3V A-weighted @ fs = 96kHz, AVDD = 3.3V DNR A-weighted, -60dB full scale input 1kHz, 0dBFs 1kHz Input, 0dB gain PSRR 1kHz 100mVpp 20Hz to 20kHz 100mVp-p Supply Current Analogue supply current Digital Supply Current AVDD = 5V DVDD = 3.3V 18.4 14.6 mA mA 95 95 1.0 x VREFP/5 103 101 101 101 Vrms dB dB dB dB
SNR (Note 1,2,4)
96
dB
Dynamic Range (Note 2,4) Total Harmonic Distortion (THD) (Note 4) Mute Attenuation DAC channel separation Power Supply Rejection Ratio
103 -90 100 100 50 45 -83
dB dB dB dB dB dB
w
PD Rev 4.1 March 2005 6
Production Data Notes: 1. 2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured `A' weighted.
WM8768
All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance). The performance of each DAC is measured separately
3. 4.
TERMINOLOGY
1. 2. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio of the rms values of (Noise + Distortion)/Signal. Stop band attenuation (dB) - Is the degree to which the frequency spectrum is attenuated (outside audio band). Channel Separation (dB) - Also known as crosstalk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. Pass-Band Ripple - Any variation of the frequency response in the pass-band region.
3. 4. 5. 6.
w
PD Rev 4.1 March 2005 7
WM8768
MASTER CLOCK TIMING
t MCLKL MCLK tMCLKH t MCLKY
Production Data
Figure 1 DAC Master Clock Timing Requirements Test Conditions o AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN = 0V, DGND = 0V, TA = +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time MCLK Duty cycle Power-saving mode activated Normal mode resumed Table 1 Master Clock Timing Requirements Note: If MCLK period is longer than maximum specified above, power-saving mode is entered and DACs are powered down with internal digital audio filters being reset. In this power-saving mode, all registers will retain their values and can be accessed in the normal manner through the control interface. Once MCLK is restored, the DACs are automatically powered up, but a write to the volume update register bit is required to restore the correct volume settings. After MCLK stopped After MCLK re-started tMCLKH tMCLKL tMCLKY 11 11 28 40:60 2 0.5 1000 60:40 10 1 Us MCLK cycle ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL AUDIO INTERFACE - MASTER MODE
BCLK WM8768 DAC LRCLK DIN1/2/3/4
4
DSP/ DECODER
Figure 2 Audio Interface - Master Mode
w
PD Rev 4.1 March 2005 8
Production Data
WM8768
BCLK (Output) tDL LRCLK (Output) DIN1/2/3/4 tDST
Figure 3 Digital Audio Data Timing - Master Mode Test Conditions o AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25 C, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER LRCLK propagation delay from BCLK falling edge DIN1/2/3/4 setup time to BCLK rising edge DIN1/2/3/4 hold time from BCLK rising edge SYMBOL tDL tDST tDHT TEST CONDITIONS MIN 0 10 10 TYP MAX 10 UNIT ns ns ns
tDHT
Audio Data Input Timing Information
Table 2 Digital Audio Data Timing - Master Mode
DIGITAL AUDIO INTERFACE - SLAVE MODE
BCLK WM8768 DAC LRCLK DIN1/2/3/4
4
DSP/ DECODER
Figure 4 Audio Interface - Slave Mode
w
PD Rev 4.1 March 2005 9
WM8768
tBCH BCLK tBCY LRCLK tDS DIN1/2/3/4 tLRH tLRSU tBCL
Production Data
Figure 5 Digital Audio Data Timing - Slave Mode
Test Conditions AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER BCLK cycle time BCLK pulse width high BCLK pulse width low LRCLK set-up time to BCLK rising edge LRCLK hold time from BCLK rising edge DIN1/2/3/4 set-up time to BCLK rising edge DIN1/2/3/4 hold time from BCLK rising edge SYMBOL tBCY tBCH tBCL tLRSU tLRH tDS tDH TEST CONDITIONS MIN 50 20 20 10 10 10 10 TYP MAX UNIT ns ns ns ns ns ns ns
Audio Data Input Timing Information
Table 3 Digital Audio Data Timing - Slave Mode
w
PD Rev 4.1 March 2005 10
Production Data
WM8768
MPU INTERFACE TIMING
tCSL ML/I2S tSCY tSCH MC/IWL tSCL tSCS tCSS
tCSH
MD/DM tDSU tDHO
LSB
Figure 6 SPI Compatible Control Interface Input Timing Test Conditions AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated PARAMETER MC/IWL rising edge to ML/I2S rising edge MC/IWL pulse cycle time MC/IWL pulse width low MC/IWL pulse width high MD/DM to MC/IWL set-up time MC/IWL to MD/DM hold time ML/I2S pulse width low ML/I2S pulse width high ML/I2S rising to MC/IWL rising SYMBOL tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS MIN 60 80 30 30 20 20 20 20 20 TYP MAX UNIT ns ns ns ns ns ns ns ns ns
Table 4 3-wire SPI Compatible Control Interface Input Timing Information
w
PD Rev 4.1 March 2005 11
WM8768 INTERNAL POWER ON RESET CIRCUIT
Production Data
Figure 7 Internal Power on Reset Circuit Schematic The WM8768 includes an internal Power-On-Reset Circuit, as shown in Figure 7, which is used reset the digital logic into a default state after power up. The POR circuit is powered from DVDD and monitors DVDD. It asserts PORB low if DVDD is below a minimum threshold.
Figure 8 Typical Power-Up Sequence Figure 8 shows a typical power-up sequence. When DVDD goes above the minimum threshold, Vpord, there is enough voltage for the circuit to guarantee PORB is asserted low and the chip is held in reset. In this condition, all writes to the control interface are ignored. When DVDD rises to Vpor_on, PORB is released high and all registers are in their default state and writes to the control interface may take place. On power down, PORB is asserted low whenever DVDD drops below the minimum threshold Vpor_off. SYMBOL Vpord Vpor_on Vpor_off MIN 0.3 1.3 1.3 TYP 0.5 1.7 1.7 MAX 0.8 2.0 2.0 UNIT V V V
Table 5 Typical POR Operation (typical values, not tested)
w
PD Rev 4.1 March 2005 12
Production Data
WM8768
DEVICE DESCRIPTION
INTRODUCTION
WM8768 is a complete 8-channel DAC including digital interpolation and decimation filters and switched capacitor multi-bit sigma delta DACs with digital volume controls on each channel and output smoothing filters. The device is implemented as four separate stereo DACs in a single package and controlled by a single interface. Each stereo DAC has its own data input DIN1/2/3/4. DAC word clock LRCLK, DAC bit clock BCLK and DAC master clock MCLK are shared between them. The Audio Interface may be configured to operate in either master or slave mode. In Slave mode, LRCLK and BCLK are all inputs. In Master mode, LRCLK and BCLK are all outputs. Each DAC has its own digital volume control that is adjustable in 0.5dB steps. The digital volume controls may be operated independently. In addition, a zero cross detect circuit is provided for each DAC for the digital volume controls. The digital volume control detects a transition through the zero point before updating the volume. This minimises audible clicks and `zipper' noise as the gain values change. Control of internal functionality of the device is by 3-wire serial or pin programmable control interface. The software control interface may be asynchronous to the audio data interface as control data will be re-synchronised to the audio processing internally. Operation using master clocks of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs is provided for the DAC In Slave mode selection between clock rates is automatically controlled. Audio sample rates (fs) from less than 8ks/s up to 192ks/s are allowed for the DAC, provided the appropriate master clock is input. In PCM mode, the audio data interface supports right justified, left justified and I S (Philips left justified, one bit delayed) interface formats along with a highly flexible DSP serial port interface.
2
PCM AUDIO DATA SAMPLING RATES
In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system's Master Clock. The external master system clock can be applied directly through the DAC MCLK input pin(s) with no software configuration necessary The DAC master clock for WM8768 supports audio sampling rates from 128fs to 1152fs, where fs is the audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz, 96kHz or 192kHz. The master clock is used to operate the digital filters and the noise shaping circuits. In Slave mode the WM8768 has a master clock detection circuit that automatically determines the relationship between the system clock frequency and the sampling rate (to within +/- 32 master clocks). If there is a greater than 32 clocks error the interface defaults to 1152fs mode. The WM8768 is tolerant of phase variations or jitter on the master clock. Table 6 shows the typical master clock frequency inputs for the WM8768. The signal processing for the WM8768 typically operates at an oversampling rate of 128fs. The exception to this is for operation with a 128/192fs system clock, e.g. for 192kHz operation, when the oversampling rate is 64fs.
w
PD Rev 4.1 March 2005 13
WM8768
SAMPLING RATE (LRCLK) 32kHz 44.1kHz 48kHz 96kHz 192kHz SYSTEM CLOCK FREQUENCY (MHZ) 128fs 4.096 5.6448 6.144 12.288 24.576 192fs 6.144 8.467 9.216 18.432 36.864 256fs 8.192 11.2896 12.288 24.576 Unavailable 384fs 12.288 16.9340 18.432 36.864 Unavailable 512fs 16.384 22.5792 24.576 Unavailable Unavailable 768fs 24.576 33.8688 36.864 Unavailable Unavailable
Production Data
1152fs 36.864 Unavailable Unavailable Unavailable Unavailable
Table 6 System Clock Frequencies Versus Sampling Rate
HARDWARE CONTROL MODES
When the MODE pin is held high, the following hardware modes of operation are available.
MUTE AND AUTOMUTE OPERATION
In both hardware and software modes, the MUTE pin controls the selection of MUTE directly, and can be used to enable and disable the automute function. This pin becomes an output when left floating and indicates infinite zero detect (IZD) has been detected. DESCRIPTION 0 1 Floating Normal Operation Mute DAC channels Enable IZD, MUTE pin becomes an output to indicate when IZD occurs. L=IZD not detected, H=IZD detected.
Table 7 Mute and Automute Control Figure 9 shows the application and release of MUTE whilst a full amplitude sinusoid is being played at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to decay exponentially from the DC level of the last input sample. The output will decay towards VMID with a time constant of approximately 64 input samples. When MUTE is de-asserted, the output will restart almost immediately from the current input sample.
1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006
Figure 9 Application and Release of Soft Mute
w
PD Rev 4.1 March 2005 14
Production Data
WM8768
In hardware mode (MODE pin set high) the MUTE pin becomes a bi-directional pin. Therefore if it is driven low the device will never softmute. If it is driven high then all channels will softmute immediately. However if the pin is connected to a high impedance, or left floating, then when all four internal zero flags are raised. the WM8768 will also drive a weak logic high signal on the MUTE pin (output impedance 10kOhms) which can be used to drive an external device. It is not possible to perform analogue mute in Hardware mode.
Figure 10 MUTE Logic in Hardware Mode
INPUT FORMAT SELECTION
In hardware mode, ML/I2S and MC/IWL become input controls for selection of input data format type and input data word length for the DAC. ML/I2S 0 0 1 1 Table 8 Input Format Selection Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that the left/right clocks (LRCLK) are high for a minimum of 24 bit clocks (BCLK) and low for a minimum of 24 bit clocks. If exactly 32 bit clocks occur in one left/right clock (16 high, 16 low) the chip will auto detect and run a 16 bit data mode. MC/IWL 0 1 0 1 INPUT DATA MODE 24-bit right justified 20-bit right justified 16-bit I S 24-bit I2S
2
DE-EMPHASIS CONTROL
In hardware mode, the MD/DM pin becomes an input control for selection of de-emphasis filtering to be applied. MD/DM 0 1 Table 9 De-emphasis Control DE-EMPHASIS Off On
w
PD Rev 4.1 March 2005 15
WM8768
DIGITAL AUDIO INTERFACE
MASTER AND SLAVE MODES
Production Data
The audio interface operates in either Slave or Master mode, selectable using the MS control bit. In both Master and Slave modes DIN1/2/3/4 are always inputs to the WM8768. The default is Slave mode. In Slave mode, LRCLK and BCLK are inputs to the WM8768 (Figure 11). DIN1/2/3/4 and LRCLK are sampled by the WM8768 on the rising edge of BCLK. By setting the control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3/4 and LRCLK are sampled on the falling edge of BCLK .
BCLK WM8768 DAC LRCLK DIN1/2/3/4
4
DSP/ DECODER
Figure 11 Slave Mode In Master mode, LRCLK and BCLK are outputs from the WM8768 (Figure 12). LRCLK and BCLK are generated by the WM8768. DIN1/2/3/4 are sampled by the WM8768 on the rising edge of BCLK so the controller must output DAC data that changes on the falling edge of BCLK. By setting control bit BCP the polarity of BCLK may be reversed so that DIN1/2/3/4 are sampled on the falling edge of BCLK..
BCLK WM8768 DAC LRCLK DIN1/2/3/4
4
DSP/ DECODER
Figure 12 Master Mode
w
PD Rev 4.1 March 2005 16
Production Data
WM8768
AUDIO INTERFACE FORMATS
Audio data is applied to the internal DAC filters via the Digital Audio Interface. 5 popular interface formats are supported: * * * * * Left Justified mode Right Justified mode I2S mode DSP mode A DSP mode B
All 5 formats send the MSB first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit right justified mode, which is not supported. In left justified, right justified and I2S modes, the digital audio interface receives DAC data on the DIN1/2/3/4 inputs. Audio data for each stereo channel is time multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used as a timing reference to indicate the beginning or end of the data words. In left justified, right justified and I2S modes, the minimum number of BCLKs per LRCLK period is 2 times the selected word length. LRCLK must be high for a minimum of word length BCLKs and low for a minimum of word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the above requirements are met. In DSP modes A or B, all 8 DAC channels are time multiplexed onto DIN1. LRCLK is used as a frame sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK period is 8 times the selected word length. Any mark to space ratio is acceptable on LRCLK provided the rising edge is correctly positioned.
LEFT JUSTIFIED MODE
In left justified mode, the MSB of DIN1/2/3/4 is sampled by the WM8768 on the first rising edge of BCLK following a LRCLK transition. LRCLK is high during the left samples and low during the right samples (Figure 13).
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
DIN1/2/3/4
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 13 Left Justified Mode Timing Diagram
w
PD Rev 4.1 March 2005 17
WM8768
RIGHT JUSTIFIED MODE
Production Data
In right justified mode, the LSB of DIN1/2/3/4 is sampled by the WM8768 on the rising edge of BCLK preceding a LRCLK transition. LRCLK are high during the left samples and low during the right samples (Figure 14).
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
DIN1/2/3/4
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 14 Right Justified Mode Timing Diagram
I2S MODE
In I2S mode, the MSB of DIN1/2/3/4 is sampled by the WM8768 on the second rising edge of BCLK following a LRCLK transition. LRCLK are low during the left samples and high during the right samples.
1/fs
LEFT CHANNEL LRCIN
RIGHT CHANNEL
BCKIN
1 BCKIN 1 BCKIN 3 n-2 n-1 n 1 2 3 n-2 n-1 n
DIN1/2/3/4
1
2
MSB
LSB
MSB
LSB
Figure 15 I2S Mode Timing Diagram
DSP MODE A
In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8768 on the second rising edge on BCLK following a LRCLK rising edge. DAC channel 1 right and DAC channels 2/3/4 data follow DAC channel 1 left data (Figure 16).
1 BCKIN 1/fs
1 BCKIN
LRCIN
BCKIN CHANNEL 1 LEFT DIN1
1 2 n-1 n 1 2
CHANNEL 1 RIGHT
n-1 n
CHANNEL 2 LEFT
1 2
CHANNEL 4 RIGHT
n-1 n
NO VALID DATA
MSB
LSB
Input Word Length (IWL)
Figure 16 DSP Mode A Timing Diagram - DAC data input
w
PD Rev 4.1 March 2005 18
Production Data
WM8768
DSP MODE B
In DSP mode B, the MSB of DAC channel 1 left data is sampled by the WM8768 on the first BCLK rising edge following a LRCLK rising edge. DAC channel 1 right and DAC channels 2/3/4 data follow DAC channel 1 left data (Figure 17).
1/fs
LRCIN
BCKIN CHANNEL 1 LEFT DIN1
1 2 n-1 n 1 2
CHANNEL 1 RIGHT
n-1 n
CHANNEL 2 LEFT
1 2
CHANNEL 4 RIGHT
n-1 n
NO VALID DATA
1
MSB
LSB
Input Word Length (IWL)
Figure 17 DSP Mode B Timing Diagram - DAC data input In both DSP modes A and B, DACL1 is always sent first, followed immediately by DACR1 and the data words for the other 8 channels. No BCLK edges are allowed between the data words. The word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right, DAC4 left, DAC4 right .
POWERDOWN MODES
The WM8768 has powerdown control bits allowing specific parts of the WM8768 to be powered off when not being used. The four stereo DACs each have a separate powerdown control bit, DACD[2:0] & DACD4, allowing individual stereo DACs to be powered off when not in use. Setting DACD will power down everything except the reference VMID. This may be powered down by setting PDWN. Setting PDWN will override all other powerdown control bits. It is recommended that the DACs are powered down before setting PDWN.
w
PD Rev 4.1 March 2005 19
WM8768
SOFTWARE CONTROL INTERFACE OPERATION
Production Data
The WM8768 is controlled using a 3-wire serial interface in software mode or pin programmable in hardware mode. The control mode is selected by the state of the MODE pin.
3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
MD/DM is used for the program data, MC/IWL is used to clock in the program data and ML/I2S is used to latch the program data. MD/DM is sampled on the rising edge of MC/IWL. The 3-wire interface protocol is shown in Figure 18.
ML/I2S
MC/IWL
MD/DM
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 18 3-wire SPI Compatible Interface 1. 2. 3. B[15:9] are Control Address Bits B[8:0] are Control Data Bits ML/I2S is edge sensitive - the data is latched on the rising edge of ML/I2S.
CONTROL INTERFACE REGISTERS
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and right channel DACs from the next audio input sample. No update to the attenuation registers is required for ATC to take effect. REGISTER ADDRESS 0000010 DAC Channel Control BIT 3 LABEL ATC DEFAULT 0 DESCRIPTION Attenuator Control Mode: 0 : Right channels use Right attenuations 1: Right Channels use Left Attenuations
w
PD Rev 4.1 March 2005 20
Production Data
WM8768
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are applied to the left and right DACs: REGISTER ADDRESS 0000010 DAC Control BIT 8:5 LABEL PL[3:0] DEFAULT 1001 PL[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DESCRIPTION Left Output Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Mute Left Right (L+R)/2 Right Output Mute Mute Mute Mute Left Left Left Left Right Right Right Right (L+R)/2 (L+R)/2 (L+R)/2 (L+R)/2
DAC DIGITAL AUDIO INTERFACE CONTROL REGISTER
Interface format is selected via the FMT[1:0] register bits: REGISTER ADDRESS 0000011 Interface Control BIT 1:0 LABEL FMT [1:0] DEFAULT 00 DESCRIPTION Interface format Select 00 : right justified mode 01: left justified mode 10: I2S mode 11: DSP Modes A or B
In left justified, right justified or I2S modes, the LRP register bit controls the polarity of LRCLK. If this bit is set high, the expected polarity of LRCLK will be the opposite of that shown Figure 13, Figure 14 and Figure 15. Note that if this feature is used as a means of swapping the left and right channels, a 1 sample phase difference will be introduced. In DSP modes, the LRP register bit is used to select between modes A and B. REGISTER ADDRESS 0000011 Interface Control BIT 2 LABEL LRP DEFAULT 0 DESCRIPTION In left/right/I2S modes: LRCLK Polarity (normal) 0 : normal LRCLK polarity 1: inverted LRCLK polarity In DSP mode: 0 : DSP mode A 1: DSP mode B
w
PD Rev 4.1 March 2005 21
WM8768
Production Data By default, LRCLK and DIN1/2/3/4 are sampled on the rising edge of BCLK and should ideally change on the falling edge. Data sources that change LRCLK and DIN1/2/3/4 on the rising edge of BCLK can be supported by setting the BCP register bit. Setting BCP to 1 inverts the polarity of BCLK to the inverse of that shown in Figure 13, Figure 14, Figure 15, Figure 16, Figure 17 and Figure 18. REGISTER ADDRESS 0000011 Interface Control BIT 3 LABEL BCP DEFAULT 0 DESCRIPTION BCLK Polarity 0 : normal BCLK polarity 1: inverted BCLK polarity
The IWL[1:0] bits are used to control the input word length. REGISTER ADDRESS 0000011 Interface Control BIT 5:4 LABEL IWL [1:0] DEFAULT 00 DESCRIPTION Input Word Length 00 : 16 bit data 01: 20 bit data 10: 24 bit data 11: 32 bit data
Note: If 32-bit mode is selected in right justified mode, the WM8768 defaults to 24 bits. In all modes, the data is signed 2's complement. The digital filters always input 24-bit data. If the DAC is programmed to receive 16 or 20 bit data, the WM8768 pads the unused LSBs with zeros. If the DAC is programmed into 32 bit mode, the 8 LSBs are ignored. Note: In 24 bit I2S mode, any width of 24 bits or less is supported provided that LRCLK is high for a minimum of 24 BCLKs and low for a minimum of 24 BCLKs. If exactly 32 bit clocks occur in one left/right clock (16 high, 16 low) the chip will auto detect and run a 16 bit data mode. A number of options are available to control how data from the Digital Audio Interface is applied to the DAC channels.
DAC OUTPUT PHASE
The DAC phase control word determines whether the output of each DAC is non-inverted or inverted REGISTER ADDRESS 0000011 DAC Phase BIT 8:6 LABEL PHASE [2:0] DEFAULT 000 Bit 0 1 2 0001111 DAC4 Control 3 PHASE4 0 N/A DESCRIPTION DAC DAC1L/R DAC2L/R DAC3L/R DAC4L/R Phase 1 = invert 1 = invert 1 = invert 1 = invert
DIGITAL ZERO CROSS-DETECT
The digital volume control also incorporates a zero cross detect circuit which detects a transition through the zero point before updating the digital volume control with the new volume. This is enabled by control bit DZCEN. REGISTER ADDRESS 0001001 DAC Control BIT 0 LABEL DZCEN DEFAULT 0 DESCRIPTION DAC Digital Volume Zero Cross Enable: 0: Zero cross detect enabled 1: Zero cross detect disabled
w
PD Rev 4.1 March 2005 22
Production Data
WM8768
SOFTMUTE
The digital muting function used in Software and Hardware mode applies a softmute with the operating characteristics shown in Figure 19.
1.5 1 0.5 0 -0.5 -1 -1.5 -2 -2.5 0 0.001 0.002 0.003 Time(s) 0.004 0.005 0.006
Figure 19 Soft Mute Operation When the softmute is applied the output of the device will decay towards VMID with a time constant of approximately 64 input samples. When the mute is released, either manually or automatically by the chip, the output will restart immediately from the current input sample.
ANALOGUE MUTE
Analogue mute can only be used in software mode and will cause the output of the selected DAC to perform an analogue mute that clamps the output of the DAC to VMID. This function is dependent in the IZD bit which is described in section INFINITE ZERO DETECT, later.
w
PD Rev 4.1 March 2005 23
WM8768
SOFTWARE MUTE MODES
Production Data
The WM8768 can be muted in a number of different ways when in software mode (MODE pin pulled low). Refer to Figure 20 which shows a representation of the interaction between functions described below.
DMUTE4, DMUTE(2:0)
MUTEALL
MUTE (register) decode
MPD
DZFM selector
Channel1 Softmute
Channel2 Softmute
Channel3 Softmute DIN1 DIN2 DIN3 DIN4 1024 Zeros Detect zflag1 zflag2 zflag3 zflag4 Channel1 Analogue Mute Channel2 Analogue Mute Channel3 Analogue Mute Channel3 Analogue Mute Channel4 Softmute
MUTE (pin)
10kOhm
IZD
Figure 20 Internal Mute Logic
w
PD Rev 4.1 March 2005 24
Production Data
WM8768
DMUTE AND MUTEALL
The WM8768 can be directly muted using the DMUTE and DMUTE4 register bits to control which channels are muted. The mute happens as soon as the serial write is performed. REGISTER ADDRESS 0001001 DAC Mute 0001111 DAC4 Control BIT 5:3 2 LABEL DMUTE [2:0] DMUTE4 DEFAULT 000 0 DESCRIPTION DAC 3,2 and 1 Soft Mute select DAC 4 Soft Mute select
{DMUTE4,DMUTE [2:0]} 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Table 10 DAC Mute Control
DAC CHANNEL 4 Not MUTE Not MUTE Not MUTE Not MUTE Not MUTE Not MUTE Not MUTE Not MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE
DAC CHANNEL 3 Not MUTE Not MUTE Not MUTE Not MUTE MUTE MUTE MUTE MUTE Not MUTE Not MUTE Not MUTE Not MUTE MUTE MUTE MUTE MUTE
DAC CHANNEL 2 Not MUTE Not MUTE MUTE MUTE Not MUTE Not MUTE MUTE MUTE Not MUTE Not MUTE MUTE MUTE Not MUTE Not MUTE MUTE MUTE
DAC CHANNEL 1 Not MUTE MUTE Not MUTE MUTE Not MUTE MUTE Not MUTE MUTE Not MUTE MUTE Not MUTE MUTE Not MUTE MUTE Not MUTE MUTE
An overall MUTE to all channels can be applied by using the MUTEALL register. REGISTER ADDRESS 0000010 DAC Mute BIT 0 LABEL MUTEALL DEFAULT 0 DESCRIPTION Soft Mute Select: 0 : Normal operation 1: Soft mute all channels
w
PD Rev 4.1 March 2005 25
WM8768
MUTE PIN AS INPUT
Production Data
The WM8768 can be muted externally by driving the MUTE pin high. When the MUTE pin is driven low the device will never automute, although direct mutes can still be applied via the DMUTE or MUTEALL registers. The DZFM bits are used to decode the operation of a MUTE pin (decides which channels will be affected by the logic level present on the MUTE pin). MPD (Mute Pin Decode) is used to enable the DZFM operation. If MPD is set, the selection made by the DZFM bits will be ignored and all channels will be muted when the pin is driven high. Table 11 below describes which channels will be softmuted when the MUTE pin is driven high depending on the MPD and DZFM bits. MPD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 {DZFM4,DZFM [1:0]} 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 CHANNELS MUTED WHEN MUTE PIN HIGH All Channels CH1 CH2 CH3 CH4 CH1 and CH2 CH1, CH2 and CH3 CH3 and CH4 All Channels All Channels All Channels All Channels All Channels All Channels All Channels All Channels
Table 11 Mute Pin Decode when Mute Pin as Input
w
PD Rev 4.1 March 2005 26
Production Data
WM8768
AUTOMUTE
The WM8768 can automute by counting zero samples on the DIN1/2/3/4 inputs. When 1024 zero samples are counted on one channel, one of four internal zero flags (zflag1/2/3/4 shown in figure 2) is raised. Depending on the external hardware and settings of DZFM, MPD and IZD, different automute operations are possible.
MUTE PIN AS OUTPUT
If the MUTE pin is connected to a high impedance (input to external mute circuitry for example) or left floating, zflag1/2/3/4 will be output on the Mute pin dependent on DZFM settings. This is described in Table 12 below. The output impedance of the MUTE pin is 10kOhms {DZFM4,DZFM [1:0]} 000 001 010 011 100 101 110 111 CONDITION UNDER WHICH MUTE PIN DRIVEN HIGH Zflag1, 2, 3 and 4 all high Zflag1 high Zflag2 high Zflag3 high Zflag4 high Zflag1 and 2 high Zflag1, 2 and 3 high Zflag3 and 4 high
Table 12 Effect of DZFM on Mute Pin Output When the Mute pin is used as an output, its logic level remains connected to the DZFM selector inside the chip (see figure 1). So, when the WM8768 drives the Mute pin high, the output DACs will also softmute as described by Table 13. MPD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 {DZFM4,DZFM [1:0]} 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 CHANNELS MUTED WHEN MUTE PIN DRIVEN HIGH All Channels CH1 CH2 CH3 CH4 CH1 and CH2 CH1, CH2 and CH3 CH3 and CH4 All Channels All Channels All Channels All Channels All Channels All Channels All Channels All Channels
Table 13 Mute Pin Decode when Mute Pin as Output
w
PD Rev 4.1 March 2005 27
WM8768
INFINITE ZERO DETECT
Production Data
When it is set, the IZD register causes an analogue mute of the DAC channel output amplifier both when there are 1024 zeros on that channel's DIN pin or when it is manually muted by DMUTE or MUTEALL. REGISTER ADDRESS 0000010 DAC Channel Control BIT 4 LABEL IZD DEFAULT 0 DESCRIPTION IZD Enable 0 : Disable infinite zero mute 1: Enable infinite zero mute
This operation is only available in software mode and can sometimes create a very small click at the output of the device.
DE-EMPHASIS MODE
Each stereo DAC channel has an individual de-emphasis control bit: REGISTER ADDRESS 0001001 DAC De-emphahsis Control 0001111 DAC4 Control BIT [8:6] LABEL DEEMPH [2:0] DEEMPH4 DEFAULT 000 DESCRIPTION DAC 3, 2 and 1 De-emphasis channel selection select: DAC 4 De-emphasis channel selection select:
4
0
{DEEMPH4,DEEMPH [2:0]} 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
DAC CHANNEL 4 Not-DEEMPH Not-DEEMPH Not-DEEMPH Not-DEEMPH Not-DEEMPH Not-DEEMPH Not-DEEMPH Not-DEEMPH DEEMPH DEEMPH DEEMPH DEEMPH DEEMPH DEEMPH DEEMPH DEEMPH
DAC CHANNEL 3 Not-DEEMPH Not-DEEMPH Not-DEEMPH Not-DEEMPH DEEMPH DEEMPH DEEMPH DEEMPH Not-DEEMPH Not-DEEMPH Not-DEEMPH Not-DEEMPH DEEMPH DEEMPH DEEMPH DEEMPH
DAC CHANNEL 2 Not-DEEMPH Not-DEEMPH DEEMPH DEEMPH Not-DEEMPH Not-DEEMPH DEEMPH DEEMPH Not-DEEMPH Not-DEEMPH DEEMPH DEEMPH Not-DEEMPH Not-DEEMPH DEEMPH DEEMPH
DAC CHANNEL 1 Not-DEEMPH DEEMPH Not-DEEMPH DEEMPH Not-DEEMPH DEEMPH Not-DEEMPH DEEMPH Not-DEEMPH DEEMPH Not-DEEMPH DEEMPH Not-DEEMPH DEEMPH DEEMPH DEEMPH
Table 14 De-emphasis Control Refer to Figure 25, Figure 26, Figure 27, Figure 28, Figure 29 and Figure 30 for details of the DeEmphasis performance at different sample rates.
REGISTER ADDRESS 0000010 DAC DEEMPH
BIT 1
LABEL DEEMP ALL
DEFAULT 0
DESCRIPTION DEEMPH Select: 0 : Normal Operation 1: De-emphasis all channels
w
PD Rev 4.1 March 2005 28
Production Data
WM8768
POWERDOWN MODE AND DAC DISABLE
Setting the PDWN register bit immediately powers down the DACs on the WM8768, overriding the DACD powerdown bits control bits. All trace of the previous input samples is removed, but all control register settings are preserved. When PDWN is cleared the digital filters will be reinitialised REGISTER ADDRESS 0000010 Powerdown Control BIT 2 LABEL PDWN DEFAULT 0 DESCRIPTION Power Down all DAC's Select: 0: All DACs enabled 1: All DACs disabled
The DACs may also be powered down individually by setting the DACPD disable bits. Each Stereo DAC channel has a separate disable DACPD[2:0]. Setting DACPD for a channel will disable the DACs and select a low power mode. REGISTER ADDRESS 0001010 Powerdown Control 0001111 DAC4 Control BIT 3:1 1 LABEL DACD[2:0] DACD4 DEFAULT 000 0 DESCRIPTION DAC Disable DAC 4 Powerdown
{DACD4,DACD [2:0]} 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
DAC CHANNEL 4 Active Active Active Active Active Active Active Active DISABLE DISABLE DISABLE DISABLE DISABLE DISABLE DISABLE DISABLE
DAC CHANNEL 3 Active Active Active Active DISABLE DISABLE DISABLE DISABLE Active Active Active Active DISABLE DISABLE DISABLE DISABLE
DAC CHANNEL 2 Active Active DISABLE DISABLE Active Active DISABLE DISABLE Active Active DISABLE DISABLE Active Active DISABLE DISABLE
DAC CHANNEL 1 Active DISABLE Active DISABLE Active DISABLE Active DISABLE Active DISABLE Active DISABLE Active DISABLE Active DISABLE
Table 15 DAC Disable Control
MASTER POWERDOWN
Control bit PWRDNALL overrides the {DACD4,DACD[2:0]} bits and powers everything down including the reference VMID. It is recommended that the DACs are powered down first before setting this bit. REGISTER ADDRESS 0001010 Interface Control BIT 4 LABEL PWRDNALL DEFAULT 0 DESCRIPTION Master Power down bit 0: Not powered down 1: Powered down
w
PD Rev 4.1 March 2005 29
WM8768
MASTER MODE SELECT
Production Data
Control bit MS selects between audio interface Master and Slave Modes. In Master mode LRCLK and BCLK are outputs and are generated by the WM8768. In Slave mode LRCLK and BCLK are inputs to WM8768. REGISTER ADDRESS 0001010 Interface Control BIT 5 LABEL MS DEFAULT 0 DESCRIPTION Audio Interface Master/Slave Mode select: 0: Slave Mode 1: Master Mode
MASTER MODE LRCLK FREQUENCY SELECT
In Master mode the WM8768 generates LRC and BCLK. These clocks are derived from the master clock and the ratio of MCLK to LRCK is set by RATE. REGISTER ADDRESS 0001010 Interface Control BIT 8:6 LABEL RATE[2:0] DEFAULT 010 DESCRIPTION Master Mode MCLK: LRCLK ratio select: 000: 128fs 001: 192fs 010: 256fs 011: 384fs 100: 512fs 101: 768fs
MUTE PIN DECODE
The MUTE pin can either be used as an output or an input. When used as an input the MUTE pins action can be controlled by setting the DZFM and DZFM4 bit to select the corresponding DAC for applying the MUTE to. As an output its meaning is selected by the DZFM and DZFM4 control bits. By default selecting the MUTE pin to represent if DAC1 has received more than 1024 midrail samples will cause the MUTE pin to assert a softmute on DAC1. Disabling the decode block will cause any logical high on the MUTE pin to apply a softmute to all DAC's. For compatibility with the WM8772 register the MUTE pin decode bit is also found in the ADC control register, which is redundant on this chip. The OR of these two register bit is taken internally. REGISTER ADDRESS 0001100 ADC Control 0001111 DAC4 control BIT 6 LABEL MPD DEFAULT 0 DESCRIPTION MUTE pin decode disable: 0: MUTE pin decode enable 1: MUTE pin decode disable MUTE pin decode disable: 0: MUTE pin decode enable 1: MUTE pin decode disable
5
MPD
0
w
PD Rev 4.1 March 2005 30
Production Data
WM8768
DAC DIGITAL VOLUME CONTROL
The DAC volume may also be adjusted in the digital domain using independent digital attenuation control registers
REGISTER ADDRESS 0000000 Digital Attenuation DACL1
BIT 7:0 8
LABEL LDA1[7:0] UPDATE
DEFAULT 11111111 (0dB) Not latched
DESCRIPTION Digital Attenuation data for Left channel DACL1 in 0.5dB steps. See Table 16 Controls simultaneous update of all Attenuation Latches 0: Store LDA1 in intermediate latch (no change to output) 1: Store LDA1 and update attenuation on all channels Digital Attenuation data for Right channel DACR1 in 0.5dB steps. See Table 16 Controls simultaneous update of all Attenuation Latches 0: Store RDA1 in intermediate latch (no change to output) 1: Store RDA1 and update attenuation on all channels. Digital Attenuation data for Left channel DACL2 in 0.5dB steps. See Table 16 Controls simultaneous update of all Attenuation Latches 0: Store LDA2 in intermediate latch (no change to output) 1: Store LDA2 and update attenuation on all channels. Digital Attenuation data for Right channel DACR2 in 0.5dB steps. See Table 16 Controls simultaneous update of all Attenuation Latches 0: Store RDA2 in intermediate latch (no change to output) 1: Store RDA2 and update attenuation on all channels. Digital Attenuation data for Left channel DACL3 in 0.5dB steps. See Table 16 Controls simultaneous update of all Attenuation Latches 0: Store LDA3 in intermediate latch (no change to output) 1: Store LDA3 and update attenuation on all channels. Digital Attenuation data for Right channel DACR3 in 0.5dB steps. See Table 16 Controls simultaneous update of all Attenuation Latches 0: Store RDA3 in intermediate latch (no change to output) 1: Store RDA3 and update attenuation on all channels. Digital Attenuation data for Left channel DACL4 in 0.5dB steps. See Table 16 Controls simultaneous update of all Attenuation Latches 0: Store LDA4 in intermediate latch (no change to output) 1: Store LDA4 and update attenuation on all channels. Digital Attenuation data for Right channel DACR4 in 0.5dB steps. See Table 16 Controls simultaneous update of all Attenuation Latches 0: Store RDA4 in intermediate latch (no change to output) 1: Store RDA4 and update attenuation on all channels. Digital Attenuation data for all DAC channels in 0.5dB steps. See Table 16 Controls simultaneous update of all Attenuation Latches 0: Store gain in intermediate latch (no change to output) 1: Store gain and update attenuation on all channels.
0000001 Digital Attenuation DACR1
7:0 8
RDA1[6:0] UPDATE
11111111 (0dB) Not latched
0000100 Digital Attenuation DACL2
7:0 8
LDA2[7:0] UPDATE
11111111 (0dB) Not latched
0000101 Digital Attenuation DACR2
7:0 8
RDA2[7:0] UPDATE
11111111 (0dB) Not latched
0000110 Digital Attenuation DACL3
7:0 8
LDA3[7:0] UPDATE
11111111 (0dB) Not latched
0000111 Digital Attenuation DACR3
7:0 8
RDA3[7:0] UPDATE
11111111 (0dB) Not latched
0001101 Digital Attenuation DACL4
7:0 8
LDA3[7:0] UPDATE
11111111 (0dB) Not latched
0001110 Digital Attenuation DACR4
7:0 8
RDA3[7:0] UPDATE
11111111 (0dB) Not latched
0001000 Master Digital Attenuation (all channels)
7:0 8
MASTDA [7:0] UPDATE
11111111 (0dB) Not latched
w
PD Rev 4.1 March 2005 31
WM8768
L/RDAX[7:0] 00(hex) 01(hex) : : : FE(hex) FF(hex) ATTENUATION LEVEL - dB (mute) -127.5dB : : : -0.5dB 0dB
Production Data
Table 16 Digital Volume Control Attenuation Levels
SOFTWARE REGISTER RESET
Writing to register 11111 will cause a register reset, resetting all register bits to their default values. This reset will last either 2*MCLK periods or until another write is made to the serial interface.
REGISTER MAP
The complete register map is shown below. The detailed description can be found in the relevant text of the device description. The WM8768 can be configured using the Control Interface. All unused bits should be set to `0'.
REGISTER R0(00h) R1(01h) B15 B14 0 0 0 0 B13 0 0 B12 0 0 B11 0 0 B10 0 0 B9 0 1 B8 UPDATE UPDATE B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 011111111 011111111 PDWN R2(02h) 0 0 0 0 0 1 0 PL[8:5] IZD ATC
All DAC ALL DAC All DAC
LDA1[7:0] RDA1[7:0] DEEMP MUTE
100100000
R3(03h) R4(04h) R5(05h) R6(06h) R7(07h) R8(08h) R9(09h) R10(0Ah)
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 1 1 0 0 1
1 0 1 0 1 0 1 0 0 UPDATE UPDATE 0 UPDATE UPDATE UPDATE UPDATE UPDATE
PHASE[8:6]
DACIWL[5:4]
DACBCP LDA2[7:0]
DACLRP
DACFMT[1:0]
000000000 011111111 011111111 011111111 011111111 011111111
RDA2[7:0] LDA3[7:0] RDA3[7:0] MASTDA[7:0] DEEMP[8:6] DMUTE[5:3] DACMS PWRDN ALL 0 0 DZFM[2:1] DACD[3:1] ZCD 0
000000000 010000000
DACRATE[8:6]
R12(0Ch) R13(0Dh) R14(0Eh) R15(0Fh) R31(1Fh)
0 0 0 0 0
0 0 0 0 0
0 0 0 0 1
1 1 1 1 1
1 1 1 1 1
0 0 1 1 1
0 1 0 1 1
0
MPD
0
0
0
0
000000000 011111111 011111111
LDA4[7:0] RDA4[7:0] 0 0 MPD DEEMP 4 RESET PHASE4 DMUTE 4 DZFM4 DACD4
000000000 000000000
w
PD Rev 4.1 March 2005 32
Production Data
WM8768
DIGITAL FILTER CHARACTERISTICS
PARAMETER DAC Filter Passband Passband ripple Stopband Stopband Attenuation Group Delay Table 17 Digital Filter Characteristics f > 0.555fs 0.555fs -60 21 dB fs 0.05 dB -3dB 0.487fs 0.05 dB 0.444fs TEST CONDITIONS MIN TYP MAX UNIT
DAC FILTER RESPONSES
0.2 0 0.15 -20 0.1
Response (dB)
Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100
-0.15 -0.2 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
-120
Figure 21 DAC Digital Filter Frequency Response - 44.1, 48 and 96kHz
Figure 22 DAC Digital Filter Ripple -44.1, 48 and 96kHz
0.2 0 0 -20
-0.2
Response (dB)
Response (dB)
-40
-0.4
-60
-0.6
-0.8 -80 -1 0 0.2 0.4 0.6 Frequency (Fs) 0.8 1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 23 DAC Digital Filter Frequency Response - 192kHz
Figure 24 DAC Digital filter Ripple - 192kHz
w
PD Rev 4.1 March 2005 33
WM8768
DIGITAL DE-EMPHASIS CHARACTERISTICS
0 1 0.5 -2 0
Response (dB)
Response (dB)
Production Data
-4
-0.5 -1 -1.5 -2
-6
-8 -2.5 -10 0 2 4 6 8 10 Frequency (kHz) 12 14 16 -3 0 2 4 6 8 10 Frequency (kHz) 12 14 16
Figure 25 De-Emphasis Frequency Response (32kHz)
0
Figure 26 De-Emphasis Error (32kHz)
0.4 0.3
-2 0.2
Response (dB)
Response (dB)
-4
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20
Figure 27 De-Emphasis Frequency Response (44.1kHz)
0
Figure 28 De-Emphasis Error (44.1kHz)
1 0.8
-2
0.6 0.4
Response (dB)
-4
Response (dB)
0.2 0 -0.2 -0.4
-6
-8
-0.6 -0.8
-10 0 5 10 15 Frequency (kHz) 20
-1 0 5 10 15 Frequency (kHz) 20
Figure 29 De-Emphasis Frequency Response (48kHz)
Figure 30 De-Emphasis Error (48kHz)
w
PD Rev 4.1 March 2005 34
Production Data
WM8768
APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
Figure 31 Recommended External Component Diagram
RECOMMENDED EXTERNAL COMPONENTS VALUES
COMPONENT REFERENCE C1 and C5 C2 to C4 C6 C7 C8 C9 R1 SUGGESTED VALUE 10F 0.1F 0.1F 10F 0.1F 100F 33 De-coupling for TESTREF1 Filtering for VREFP. Omit if AVDD low noise. Filtering for VREFP. Use 0 if AVDD low noise. DESCRIPTION De-coupling for DVDD and AVDD. De-coupling for DVDD and AVDD. Reference de-coupling capacitors for VMID.
Table 18 External Components Description
w
PD Rev 4.1 March 2005 35
WM8768
SUGGESTED ANALOGUE LOW PASS POST DAC FILTERS
Production Data
It is recommended that a lowpass filter be applied to the output from each DAC channel for Hi Fi applications. Typically a second order filter is suitable and provides sufficient attenuation of high frequency components (the unique low order, high bit count multi-bit sigma delta DAC structure used in WM8768 produces much less high frequency output noise than normal sigma delta DACs. This filter is typically also used to provide the 2x gain needed to provide the standard 2Vrms output level from most consumer equipment. Figure 32 shows a suitable post DAC filter circuit, with 2x gain. Alternative inverting filter architectures might also be used with as good results.
1.0nF 10uF 1.8k 7.5k
VOUT1L
47k 680pF
51
4.7k 4.7k
OP_FIL
VOUT1R VOUT2L VOUT2R VOUT3L VOUT3R VOUT4L VOUT4R
OP_FIL OP_FIL OP_FIL OP_FIL OP_FIL OP_FIL OP_FIL
Figure 32 Recommended Post DAC Filter Circuit
w
PD Rev 4.1 March 2005 36
Production Data
WM8768
PACKAGE DRAWING
DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) DM007.D
b
28
e
15
E1
E
1
D
14
GAUGE PLANE
c A A2 A1
L
0.25
L1
-C0.10 C
SEATING PLANE
Symbols A A1 A2 b c D e E E1 L L1 REF: MIN ----0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55 0
o
Dimensions (mm) NOM --------1.75 0.30 ----10.20 0.65 BSC 7.80 5.30 0.75 0.125 REF o 4 JEDEC.95, MO-150
MAX 2.0 0.25 1.85 0.38 0.25 10.50 8.20 5.60 0.95 8
o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM. D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
w
PD Rev 4.1 March 2005 37
WM8768 IMPORTANT NOTICE
Production Data
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom
Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
w
PD Rev 4.1 March 2005 38

▲Up To Search▲

Price & Availability of WM8768EDSR

	To Download WM8768EDSR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .